For portable or mobile electronic devices, such like cellular phones, tablet computers, watches and the like, it is a general aim to reduce the electric power consumption in order to prolong lifetime of a battery or to make use of rather compact rechargeable batteries that provide only limited energy storage capacities. Almost all kinds of digital electronic devices make use of a memory circuit. The U.S. Pat. No. 5,754,010 for instance discloses a Flash memory array having a memory circuit with a bit cell coupled to a bit-line and further having a pre-charge circuit that provides a pre-charge current to the bit-line during a pre-charge time. Pre-charging of numerous bit-lines in the memory array prior to a ‘read’ operation draws a large current from a portable battery for charging the capacitive load on each bit-line.
For a readout of a bit cell or memory cell, a current flowing through that particular cell is compared with a reference current by means of a sense amplifier. With conventional memory circuits such as disclosed in the U.S. Pat. No. 5,754,010, a NMOS-type multiplexer is connected with its drain to the input of the sense amplifier. The source of such a NMOS multiplexer is connected to the bit-line. Since such NMOS-type multiplexers exhibit a substantial and negligible threshold voltage, the lowest possible voltage level on the memory bit-line is limited by the voltage on the gate of such NMOS multiplexers and hence by the threshold voltage of such a NMOS transistor.
Typically, the maximum voltage on the memory bit-line Vbl is about the voltage on the gate of the NMOS multiplexer Vg minus the threshold voltage Vth of the NMOS multiplexer. So a minimum supply voltage for reading of the memory must be quite high. Since the NMOS multiplexer may also have to support a high voltage level for erasing and for writing of the at least one bit cell or memory cell, such multiplexers have to be composed of NMOS transistors that exhibit a rather high threshold voltage. A rather high threshold voltage of the NMOS multiplexer further reduces the voltage level on the memory bit-line for a given supply voltage. Moreover, a rather high threshold voltage of the NMOS multiplexer for programming a memory cell counteracts lowering of the supply voltage for reading of the stored data.
The bit-line voltage limits the memory cell current and therefore has an impact to the memory access time and minimal read voltage. The voltage on the gate of the NMOS-type multiplexer is either equal to the supply voltage of the memory circuit or it can be created by a pre-charge circuit, hence by a so called charge pump. Use and implementation of such a pre-charge circuit usually leads to a larger power consumption and requires implementation of a rather complicated control circuit, e.g. including a clock for the charge pump.